Method and system for compensating for estimated distortion in a transmitter by utilizing a digital predistortion scheme with a single feedback mixer

ABSTRACT

Aspects of a method and system for compensating for estimated distortion in a transmitter by utilizing a digital predistortion scheme with a single feedback mixer are presented. Aspects of the system may include at least one circuit that enables generation of an output signal in response to one or more generated input signals. A feedback signal may be generated within a single feedback mixer circuit that may perform a frequency mix-down operation on the generated output signal. The generated feedback signal may be inserted at one or more insertion points in a receiver. Each of the insertion points may be located between a mixer stage of the receiver, and one or more circuits that generate a baseband signal based on the generated feedback signal.

CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE

This application is a continuation of U.S. application entitled “Method and System for Compensating for Estimated Distortion in a Transmitter by Utilizing a Digital Predistortion Scheme with a Single Feedback Mixer” having Ser. No. 13/478,918, filed on May 23, 2012, which is a continuation of U.S. application entitled “Method and System for Compensating for Estimated Distortion in a Transmitter by Utilizing a Digital Predistortion Scheme with a Single Feedback Mixer” having Ser. No. 11/618,699, filed on Dec. 29, 2006, which makes reference to, claims priority to, and claims the benefit of U.S. Provisional Application Ser. No. 60/868,818, filed on Dec. 6, 2006.

The above stated applications are hereby incorporated herein by reference in their entireties.

FIELD OF THE INVENTION

Certain embodiments of the invention relate to wireless communications. More specifically, certain embodiments of the invention relate to a method and system for compensating for estimated distortion in a transmitter by utilizing a digital predistortion scheme with a single feedback mixer.

BACKGROUND OF THE INVENTION

A power amplification circuit in a wireless system is typically a large signal device. In wireless local area network (WLAN) systems, the power amplifier circuit may transmit output signals at average power levels in the range of 10 dBm to 15 dBm, and peak power levels of about 25 dBm, for example. In WLAN systems, which use OFDM or CCP modulation, output power levels may vary widely such that the ratio of the peak power level to the average power level may be large, for example, 12 dB for OFDM and 6 dB for CCK. Because of these large swings in output power levels, power amplifier (PA) circuits may distort the output signal. Distortion, however, is a characteristic, which may be observed in PA circuits that are utilized across a wide range of applications, and may not be limited to PA circuits utilized in wireless systems. There are two metrics, which may be utilized to evaluate the distortion performance of PA circuits. These metrics may be referred to as amplitude modulation to amplitude modulation (AM-AM) distortion, and amplitude modulation to phase modulation (AM-PM) distortion.

The AM-AM distortion provides a measure of the output power level, p_(out), in response to the input power level, p_(in). The input power level, and output power level are each typically measured in units of dBm, for example. In an ideal, non-distorting, PA circuit, the output power level changes linearly in response to a change in the input power level. Thus, for each Δp_(in) change in the input power level there may be a corresponding change in the output power level, Δp_(out)≈Δp_(in). The AM-AM distortion may be observed when, for example, the output power level in response to a first input power level may be p_(out1)≈αp_(in1), where the output level in response to a second input power level may be p_(out2)≈βp_(in2), when α≠β.

The AM-PM distortion provides a measure of the phase of the output signal in relation to the input signal (or output phase) in response to the input power level. Output phase is typically measured in units of angular degrees. The AM-PM distortion may be observed when, for example, the output phase changes in response to a change in input power level.

Limitations in the performance of PA circuitry due to distortion may be exacerbated when the PA is integrated in a single integrated circuit (IC) device with other radio frequency (RF) transmitter circuitry [such as digital to analog converters (DAC), low pass filters (LPF), mixers, and RF programmable gain amplifiers (RFPGA)]. Whereas the pressing need to increase the integration of functions performed within a single IC, and attendant increase in the number of semiconductor devices, may push semiconductor fabrication technologies toward increasingly shrinking semiconductor device geometries, these very semiconductor fabrication technologies may impose limitations on the performance of the integrated PA circuitry. For example, utilizing a 65 nm CMOS process may restrict the range of input power levels for which the PA provides linear output power level amplification. Specifications for AM-AM and/or AM-PM distortion levels as set forth in a WLAN standard, such as IEEE 802.11, may preclude transmitting output signals at high output power levels for PA circuitry that is fabricated utilizing a 65 nm CMOS process, for example.

One current approach utilized in an attempt to reduce AM-AM distortion and/or AM-PM distortion involves fabricating PA circuitry in discrete IC devices, which are not integrated with other RF transmitter circuitry. The fabrication processes for these IC devices may utilize gallium arsenide (GaAs) and/or gallium nitride (GaN) materials. Silicon (Si), which is a material utilized in CMOS and various other semiconductor fabrication processes offers several advantages in relation to GaAs and/or GaN. First, silicon is a readily available, and inexpensive, material. Second, Si readily bonds to a silicon dioxide (SiO₂) layer, a commonly utilized insulating layer during semiconductor manufacturing. Third, Si supports high hole mobility. Thus, Si may support high speed p-channel devices, which are utilized in conjunction with n-channel devices, in CMOS circuitry. GaAs and/or GaN may be relatively expensive materials, which may not form stable adhesion with SiO₂ layers, may not support high hole mobility when doped to form p-channel devices, and/or may become physically brittle when doped to form n-channel devices.

The discrete IC approach imposes its own limitations, however. One such limitation is that by placing the PA circuitry and other RF transmitter circuitry in discrete IC devices, each device may be required to provide external pins that enable interfacing of the discrete devices. Increasing pin count may increase the manufacturing cost of each IC device. Furthermore, additional external circuitry may be required if the interfaces between the discrete IC devices are not compatible. For example, additional external circuitry may be required if the interface from one discrete IC device utilizes single ended input and output (I/O), while the interface from another discrete IC device utilizes differential I/O.

In another current approach utilized in an attempt to reduce AM-AM distortion and/or AM-PM distortion the input power level may be restricted to a narrower range, which may in turn restrict the maximum output power level. One limitation of this approach in wireless communication systems is that restricting the maximum output power level may reduce the range over which a mobile terminal may transmit signals to, for example, a node B element of base transceiver station (BTS) in a wireless network. To the wireless network operator, the reduction in range may require that more node B elements, and/or BTSs be deployed, or risk that wireless network users will experience decreased communications quality, and/or dropped calls when communicating via the network.

Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

A method and system for compensating for estimated distortion in a transmitter by utilizing a digital predistortion scheme with a single feedback mixer, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

These and other advantages, aspects and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a block diagram illustrating and exemplary mobile terminal, which may be utilized in connection with an embodiment of the invention.

FIG. 2 is an exemplary block diagram illustrating a single chip RF transmitter and receiver utilizing a single feedback mixer, in accordance with an embodiment of the invention.

FIG. 3A is a graph illustrating an exemplary AM-AM distortion response in a transmitter power amplifier circuit, in accordance with an embodiment of the invention.

FIG. 3B is a graph illustrating an exemplary AM-PM distortion response in a transmitter power amplifier circuit, in accordance with an embodiment of the invention.

FIG. 4 is a flow chart illustrating an exemplary calibration method for estimating distortion in a transmitter, in accordance with an embodiment of the invention.

FIG. 5 is a flow chart illustrating an exemplary calibration method for estimating distortion in a transmitter for modulated data, in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Certain embodiments of the invention may be found in a method and system for compensating for estimated distortion in a transmitter by utilizing a digital predistortion scheme with a single feedback mixer. Various embodiments of the invention may comprise a system in which an input signal is generated by a baseband processor and communicated to an RF transmitter chain. The output from a PA circuit in the RF transmitter chain may be attenuated and mixed down utilizing a single feedback mixer. The mixed down signal from the single feedback mixer may then be inserted as a feedback signal in the RF receiver chain. By selecting a range of input power levels, the baseband processor may measure corresponding output power levels and output phase measurements. Based on these measurements, the baseband processor may estimate the AM-AM distortion, and/or AM-PM distortion, performance of the PA circuit. Also based on these measurements, the baseband processor may generate subsequent input signals, wherein the input power levels and/or input phase may be adjusted, or predistorted, to compensate for the estimated AM-AM distortion, and/or AM-PM distortion. The predistortion may be applied to a digital signal, and thereby may be referred to as a digital predistortion scheme.

In various embodiments of the invention, the utilization of a feedback mixer may enable bypass of RF mixers in the RF receiver chain. This may simplify the design of the RF mixers in the RF receiver chain, which may be optimized for the specific task receiving of RF signals from a wireless communications medium. Various embodiments of the invention may also enable compensation for AM-AM and/or AM-PM distortion in PA circuits, which may result from semiconductor fabrication technologies, such as 65 nm CMOS processes, for example.

FIG. 1 is a block diagram illustrating and exemplary mobile terminal, which may be utilized in connection with an embodiment of the invention. Referring to FIG. 1, there is shown a mobile terminal 120 that may comprise an RF receiver 123 a, an RF transmitter 123 b, a digital baseband processor 129, a processor 125, and a memory 127. In some embodiments of the invention, the RF receiver 123 a, and RF transmitter 123 b may be integrated into an RF transceiver 122, for example. A single transmit and receive antenna 121 may be communicatively coupled to the RF receiver 123 a and the RF transmitter 123 b. A switch 124, or other device having switching capabilities may be coupled between the RF receiver 123 a and RF transmitter 123 b, and may be utilized to switch the antenna 121 between transmit and receive functions.

The RF receiver 123 a may comprise suitable logic, circuitry, and/or code that may enable processing of received RF signals. The RF receiver 123 a may enable receiving RF signals in frequency bands utilized by various wireless communication systems, such as GSM and/or CDMA, for example.

The digital baseband processor 129 may comprise suitable logic, circuitry, and/or code that may enable processing and/or handling of baseband signals. In this regard, the digital baseband processor 129 may process or handle signals received from the RF receiver 123 a and/or signals to be transferred to the RF transmitter 123 b for transmission via a wireless communication medium. The digital baseband processor 129 may also provide control and/or feedback information to the RF receiver 123 a and to the RF transmitter 123 b, based on information from the processed signals. The digital baseband processor 129 may communicate information and/or data from the processed signals to the processor 125 and/or to the memory 127. Moreover, the digital baseband processor 129 may receive information from the processor 125 and/or to the memory 127, which may be processed and transferred to the RF transmitter 123 b for transmission via the wireless communication medium.

The RF transmitter 123 b may comprise suitable logic, circuitry, and/or code that may enable processing of RF signals for transmission. The RF transmitter 123 b may enable transmission of RF signals in frequency bands utilized by various wireless communications systems, such as GSM and/or CDMA, for example.

The processor 125 may comprise suitable logic, circuitry, and/or code that may enable control and/or data processing operations for the mobile terminal 120. The processor 125 may be utilized to control at least a portion of the RF receiver 123 a, the RF transmitter 123 b, the digital baseband processor 129, and/or the memory 127. In this regard, the processor 125 may generate at least one signal for controlling operations within the mobile terminal 120.

The memory 127 may comprise suitable logic, circuitry, and/or code that may enable storage of data and/or other information utilized by the mobile terminal 120. For example, the memory 127 may be utilized for storing processed data generated by the digital baseband processor 129 and/or the processor 125. The memory 127 may also be utilized to store information, such as configuration information, which may be utilized to control the operation of at least one block in the mobile terminal 120. For example, the memory 127 may comprise information necessary to configure the RF receiver 123 a to enable receiving RF signals in the appropriate frequency band.

FIG. 2 is an exemplary block diagram illustrating a single chip RF transmitter and receiver utilizing a single feedback mixer, in accordance with an embodiment of the invention. Referring to FIG. 2, there is shown a single chip RF transceiver 200, baluns 216 and 222, switch 124, and antenna 121. The single chip RF transceiver 200 may comprise the RF receiver 123 a, the RF transmitter 123 b, a signal attenuation block 218, a feedback mixer 220, and a baseband processor 240. The RF transmitter 123 b may comprise a power amplifier (PA) 214, a power amplifier driver (PAD) 212, an RF programmable gain amplifier (RFPGA) 210, a transmitter In-phase signal (I) mixer 208 a, a transmitter Quadrature-phase signal (Q) mixer 208 b, an I transconductance amplifier (gm) 206 a, a Q gm 206 b, an I low pass filter (LPF) 204 a, a Q LPF 204 b, an I digital-to-analog converter (I DAC) 202 a, and a Q DAC 202 b. The RF receiver 123 a may comprise an RF low noise amplifier (RFLNA) 224, a receiver I mixer 226 a, a receiver Q mixer 226 b, an I path selector switch 234 a, a Q path selector switch 234 b, an I high pass variable gain amplifier (HPVGA) 228 a, a Q HPVGA 228 b, an I LPF 230 a, a Q LPF 230 b, an I analog-to-digital converter (ADC) 232 a, and a Q ADC 232 b.

The signal attenuation block 218 may comprise suitable logic, circuitry, and/or code that may enable generation of an output signal, the amplitude and/or power level of which may be based on an input signal after insertion of a specified level of attenuation. In various embodiments of the invention the attenuation level may be programmable over a range of attenuation levels. In an exemplary embodiment of the invention, the range of attenuation levels may comprise −32 dB to −40 dB, although various embodiments of the invention may not be limited to such a specific range. In an exemplary embodiment of the invention, the signal attenuation block 218 may receive a differential input signal and output a differential output signal.

The feedback mixer 220 may comprise suitable logic, circuitry, and/or code that may enable mix down of an input signal. The feedback mixer 220 may utilize an input local oscillator signal labeled as LO₂₂₀ (in FIG. 2) to mix down the input signal. The frequency of the signal LO₂₂₀ may be selected from a frequency band utilized by a specified wireless communication system, for example WLAN—the same frequency as LO_(208a) and LO_(208b).

The PA 214 may comprise suitable logic, circuitry, and/or code that may enable amplification of input signals to generate a transmitted signal of sufficient signal power (as measured by dBm, for example) for transmission via a wireless communication medium. In an exemplary embodiment of the invention, the PA 214 may receive a differential input signal and output a differential output signal.

The PAD 212 may comprise suitable logic, circuitry, and/or code that may enable amplification of input signals to generate an amplified output signal. The PAD 212 may be utilized in multistage amplifier systems wherein the output of the PAD 212 may be an input to a subsequent amplification stage. In an exemplary embodiment of the invention, the PA 214 may receive a differential input signal and output a differential output signal.

The RFPGA 210 may comprise suitable logic, circuitry, and/or code that may enable amplification of input signals to generate an amplified output signal, wherein the amount of amplification, as measured in dB, may be determined based on an input control signal. In various embodiments of the invention, the input control signal may comprise binary bits. In an exemplary embodiment of the invention, the RFPGA 210 may receive a differential input signal and generate a differential output signal.

The transmitter I mixer 208 a may comprise suitable logic, circuitry, and/or code that may enable generation of an RF signal by upconversion of an input signal. The transmitter I mixer 208 a may utilize an input local oscillator signal labeled as LO_(208a) to upconvert the input signal. The upconverted signal may be an RF signal. The transmitter I mixer 208 a may produce an RF signal for which the carrier frequency may be equal to the frequency of the signal LO_(208a). In an exemplary embodiment of the invention, the transmitter I mixer 208 a may receive a differential input signal and generate a differential output signal.

The transmitter Q mixer 208 b may be substantially similar to the transmitter I mixer 208 a. The transmitter Q mixer 208 b may utilize an input local oscillator signal labeled as LO_(208b) in quadrature to LO_(208a) (in FIG. 2) to upconvert the input signal.

The I gm 206 a may comprise suitable, logic, circuitry, and/or code that may enable generation of an output current, the amplitude of which may be proportional to an amplitude of an input voltage, wherein the measure of proportionality may be determined based on the transconductance parameter, gm_(I), associated with the I gm 206 a. In an exemplary embodiment of the invention, the I gm 206 a may receive a differential input signal and output a differential output signal.

The Q gm 206 b may be substantially similar to the I gm 206 a. The transconductance parameter associated with the Q gm 206 b is gm_(Q).

The I LPF 204 a may comprise suitable logic, circuitry, and/or code that may enable selection of a cutoff frequency, wherein the LPF may attenuate the amplitudes of input signal components for which the corresponding frequency is higher than the cutoff frequency, while the amplitudes of input signal components for which the corresponding frequency is less than the cutoff frequency may “pass,” or not be attenuated, or attenuated to a lesser degree than input signal components at frequencies higher than the cutoff frequency. In various embodiments of the invention, the I LPF 210 a may be implemented as a passive filter, such as one that utilizes resistor, capacitor, and/or inductor elements, or implemented as an active filter, such as one that utilizes an operational amplifier. In an exemplary embodiment of the invention, the I LPF 210 a may receive a differential input signal and output a differential output signal.

The Q LPF 204 b may be substantially similar to the I LPF 204 a.

The I DAC 202 a may comprise suitable logic, circuitry, and/or code that may enable conversion of an input digital signal to a corresponding analog representation.

The Q DAC 202 b may be substantially similar to the I DAC 202 a.

The RFLNA 224 may comprise suitable logic, circuitry, and/or code that may enable amplification of weak signals (as measured by dBm, for example), such as received from an antenna. The input signal may be an RF signal received at an antenna, which is communicatively coupled to the RFLNA 224. The RFLNA 224 may typically be located in close physical proximity to the antenna to avoid further weakening of the signal received at the antenna. In an exemplary embodiment of the invention, the RFLNA 224 may receive a differential input signal and output a differential output signal.

The receiver I mixer 226 a may comprise suitable logic, circuitry, and/or code that may enable downconversion of an input signal. The receiver I mixer 226 a may utilize an input local oscillator signal labeled as LO_(226a) (in FIG. 2) to downconvert the input signal. The input signal may be an RF signal that may be downconverted to generate a baseband signal, or an intermediate frequency (IF) signal. In general, the receiver I mixer 226 a may produce signals for which the frequencies may be the sum and difference of the frequency of the input signal, the frequency of the signal LO_(226a), and/or harmonic frequencies derived from the before mentioned signals. In an exemplary embodiment of the invention, the receiver I mixer 226 a may receive a differential input signal and output a differential output signal.

The receiver Q mixer 226 b may be substantially similar to the receiver I mixer 226 a. The receiver Q mixer 226 b may utilize an input local oscillator signal labeled as LO_(226b) (in FIG. 2) to downconvert the input signal.

The I path selector switch 234 a may comprise suitable logic, circuitry, and/or code that may enable an input signal to be selectively coupled to one of a plurality of output points. In an exemplary embodiment of the invention, the I path selector switch 234 a may select from 2 pairs of differential input signals, coupling the selected differential input signal to a differential output.

The Q path selector switch 234 b may be substantially similar to the I path selector switch 234 a.

The I HPVGA 228 a may comprise suitable logic, circuitry, and/or code that may enable attenuation of input signals to generate an attenuated output signal, wherein the amount of attenuation, as measured in dB for example, may be determined based on an input control signal. In various embodiments of the invention, the input control signal may comprise binary bits. In various embodiments of the invention, the HPVGA 228 a may provide attenuation levels that range from 0 dB to −30 dB in 3 dB increments. In an exemplary embodiment of the invention, the I HPVGA 228 a may receive a differential input signal and output a differential output signal.

The I LPF 230 a and Q LPF 230 b may be substantially similar to the I LPF 204 a.

The I ADC 232 a may comprise suitable logic, circuitry, and/or code that may enable conversion of an input analog signal to a corresponding digital representation. The I ADC 232 a may receive an input analog signal, which may be characterized by a signal amplitude.

The I ADC 232 a may quantize the analog signal by correlating ranges of analog signal level values to corresponding numerical values. The I ADC 232 a may determine analog signal levels at distinct time instants by measuring, or integrating, the analog signal level of the input signal during a time interval referred to as δt. The time interval between measurements, or sampling interval, may be determined based on a sampling rate, which is typically long in comparison to the integration time interval δt. In an exemplary embodiment of the invention, the I ADC 232 a may receive a differential input signal and output a differential output signal.

The Q ADC 232 b may be substantially similar to the I ADC 232 a.

The baseband processor 240 may comprise suitable logic, circuitry, and/or code that may enable processing of binary data contained within an input baseband signal. The baseband processor 240 may perform processing tasks, which correspond to one or more layers in an applicable protocol reference model (PRM). For example, the baseband processor 240 may perform physical (PHY) layer processing, layer 1 (L1) processing, medium access control (MAC) layer processing, logical link control (LLC) layer processing, layer 2 (L2) processing, and/or higher layer protocol processing based on input binary data. The processing tasks performed by the baseband processor 240 may be referred to as being within the digital domain. The baseband processor 240 may also generate control signals based on the processing of the input binary data. In an exemplary embodiment of the invention, the baseband processor 240 may receive differential input signals and output differential output signals.

In operation, the baseband processor 240 may generate data comprising a sequence of bits to be transmitted via a wireless communications medium. The baseband processor 240 may generate control signals that configure the RF transmitter 123 b to transmit the data. The baseband processor 240 may send a portion of the data, an I_(BB) signal, to the I DAC 202 a, and another portion of the data, a Q_(BB) signal, to the Q DAC 202 b. The I DAC 202 a may receive a sequence of bits and generate an analog signal. The Q DAC 202 b may similarly generate an analog signal.

The analog signals generated by the I DAC 202 a and Q DAC 202 b may comprise undesirable frequency components. The I LPF 204 a and Q LPF 204 b may attenuate signal amplitudes associated with these undesirable frequency components in signals generated by the I DAC 202 a and Q DAC 202 b respectively. The baseband processor 240 may configure the transmitter I mixer 208 a to select a frequency for the LO_(208a) signal utilized to upconvert the filtered signal from the I LPF 204 a. The upconverted signal output from the transmitter I mixer 208 a may comprise an I component RF signal. The baseband processor 240 may similarly configure the transmitter Q mixer 208 b to generate a Q component RF signal from the filtered signal from the Q LPF 204 b.

The RFPGA 210 may amplify the I component and Q component RF signals to generate a quadrature RF signal, wherein the level of amplification provided by the RFPGA 210 may be configured based on control signals generated by the baseband processor 240. The PAD 212 may provide a second stage of amplification for the signal generated by the RFPGA 210, and the PA 214 may provide a third stage of amplification for the signal generated by the PAD 212. The amplified signal from the PA 214 may be transmitted to the wireless communications medium via the antenna 121.

The baseband processor 240 may configure the RF receiver 123 a and/or RF transmitter 123 b for two modes of operation comprising a normal operating mode, and a calibration mode. In the normal operating mode, the RF transmitter 123 b may transmit RF signals via the antenna 121, while the RF receiver 123 a may receive RF signals via the antenna 121. In the calibration mode, the RF signal output from the RF transmitter 123 b may be attenuated, mixed down, and inserted in the RF receiver 123 a as a feedback signal. Thus, the calibration mode may enable a closed feedback loop from the baseband processor 240, to the RF transmitter 123 b, to a feedback point within the RF receiver 123 a, and back to the baseband processor 240.

In a normal operating mode, the baseband processor 240 may generate control signals that enable configuration of the I path selector switch 234 a such that I path selector switch 234 a may be configured to select an input from the receiver I mixer 226 a. The I path selector switch 234 a may enable the output signal from the I mixer 226 a to be coupled to an input to the I HPVGA 228 a. The baseband processor 240 may also generate control signals that enable configuration of the Q path selector switch 234 b such that Q path selector switch 234 b may be configured to select an input from the receiver Q mixer 226 b. The Q path selector switch 234 b may enable the output signal from the Q mixer 226 b to be coupled to an input to the Q HPVGA 228 b.

In the normal operating mode, the RF receiver 123 a may receive RF signals via the antenna 121. The RFLNA 224 may amplify the received RF signal, which may then be sent to the receiver I mixer 226 a and/or receiver Q mixer 226 b. The receiver I mixer 226 a may downconvert the amplified RF signal. Similarly, the receiver Q mixer 226 b may also downconvert the amplified RF signal.

The baseband processor 240 may generate control signals that configure the I HPVGA 228 a to amplify a portion of the downconverted signal Output_(226a). In an exemplary embodiment of the invention, the I HPVGA 228 a may amplify signal components for which the corresponding frequency may be higher than baseband. Similarly, the baseband processor 240 may generate control signals that configure the Q HPVGA 228 b to attenuate a portion of the downconverted signal Output_(226b).

The I LPF 230 a may filter the amplified signal received from the I HPVGA 228 a such that the output of the I LPF 230 a is a baseband signal. The baseband signal may comprise a sequence of symbols. Similarly, the Q LPF 230 b may generate a baseband signal. The I ADC 232 a may convert an amplitude of a symbol in the baseband signal received from the I LPF 230 a to a sequence of bits. Similarly, the Q ADC 232 b may convert an amplitude of a symbol in the baseband signal received from the Q LPF 230 b to a sequence of bits. The baseband processor 240 may receive the sequence of bits from the I ADC 232 a and Q ADC 232 b and perform various processing tasks as set forth above.

In the calibration mode, the baseband processor 240 may generate control signals that enable configuration of the I path selector switch 234 a and/or Q path selector switch 234 b such that I path selector switch 234 a and/or Q path selector switch 234 b may be configured to select an input from the feedback mixer 220. The I path selector switch 234 a may enable the output signal from the feedback mixer 220 to be coupled to an input to the I HPVGA 228 a. The Q path selector switch 234 b may enable the output signal from the feedback mixer 220 to be coupled to an input to the Q HPVGA 228 b. In the exemplary block diagram shown in FIG. 2, the I path selector switch 234 a and Q path selector switch 234 b are each configured to couple an input signal from the feedback mixer 220, to the inputs for the I HPVGA 228 a, and Q HPVGA 228 b.

In the calibration mode, the output signal from the PA 214 may be input to the signal attenuation block 218. In the calibration mode, the baseband signals are unmodulated. The signal attenuation block 218 may adjust the amplitude of the RF signal generated by the PA 214 to a level more suitable for input to the feedback mixer 220. The signal attenuation block 218 may be configured by the baseband processor 240 to apply a specified attenuation level to the input signal from the PA 214. The feedback mixer 220 may mix down a attenuated RF signal to generate an Output₂₂₀ signal. In the calibration mode, the I HPVGA 228 a and/or Q HPVGA 228 b may receive input signals from the feedback mixer 220.

The I LPF 230 a may filter the amplified signal received from the I HPVGA 228 a such that the output of the I LPF 230 a may be based on the baseband component of the Output₂₂₀ signal. Similarly, the Q LPF 230 b may generate a baseband signal.

One limitation of the PA 214 is that the output signal may become increasingly distorted as the output power level from the PA 214 increases. The distortion may be detected through AM-AM distortion measurements, and/or AM-PM distortion measurements.

In various embodiments of the invention, the calibration mode may enable the baseband processor 240 to compensate for AM-AM distortion and/or AM-PM distortion. In one aspect of the invention, the calibration mode may enable the baseband processor 240 to send input signals I_(BB) and Q_(BB) to the RF transmitter 123 b, from which a quadrature RF signal may be generated as an output signal from the PA 214. The output signal from the PA 214 to be attenuated by the signal attenuation block 218, mixed down by the feedback mixer 220, and inserted into the RF receiver 123 a path as a feedback signal input to the I HPVGA 228 a and/or Q HPVGA 228 b. The feedback signal may be processed within the RF receiver 123 a path and received as one or more baseband signals, I_(FB) and/or Q_(FB), at the baseband processor 240. The baseband processor 240 may then estimate the AM-AM distortion performance of the PA 214 based on the amplitudes of the I_(FB) and/or Q_(FB) signals, and the amplitudes of the I_(BB) and Q_(BB). The baseband processor 240 may estimate the AM-PM distortion performance of the PA 214 based on the relative phase of the I_(FB) and the I_(BB) signals, and/or the relative phase of the Q_(FB) and Q_(BB) the signals. By estimating the AM-AM distortion performance and/or AM-PM distortion performance of the PA 214 for a range of input power levels for the I_(BB) and Q_(BB) signals, the baseband processor 240 may compute a characterization of the AM-AM performance and/or AM-PM performance of the PA 214 for a range of input power levels and/or output power levels.

After characterizing the AM-AM distortion performance, and/or AM-PM distortion performance of the PA 214, the baseband processor 240 may determine an intended output power level, p_(out) _(—) _(ideal), and/or relative phase, φ_(ideal), for an output generated by the PA 214 based on original power levels, p_(in) _(—) _(I) and/or p_(in) _(—) _(Q), for the input signals I_(BB) and/or Q_(BB), respectively. The intended output power level and/or relative phase may be based on an ideal PA, which may be linear across the range of input power levels and/or output power levels. The baseband processor 240 may then estimate the output power level, p_(out) _(—) _(est), and/or relative phase, φ_(est), resulting from original power levels p_(in) _(—) _(I) and/or p_(in) _(—) _(Q) based on the characterization of the PA 214. The baseband processor 240 may adjust the original power levels for the input signals I_(BB) and/or Q_(BB) to select adjusted input power levels adj_p_(in) _(—) _(I) and/or adj_p_(in) _(—) _(Q) that produce the intended output power level p_(out) _(—) _(deal) based on the characterization.

The baseband processor 240 may then adjust the relative phase by adjusting the time instant at which the input signals I_(BB) and/or Q_(BB) are sent to the RF transmitter 123 b. The relative phase adjustment may be determined by adjusting the time instant relative to a scheduled time instant, t₀. Based on the relative phase adjustment, either or both the input signals I_(BB) and/or Q_(BB) may be sent to the RF transmitter 123 b at a time instant, t⁰⁻, which may be a time instant that occurs earlier than the scheduled time instant, or a time instant, t₀₊, which may be a time instant that occurs later in time than the scheduled time instant. The relative phase adjustment for each input signal I_(BB) and/or Q_(BB) may be selected such that the relative phase of the output signal from the PA 214 may be approximately constant for a range of input power levels for the input signals I_(BB) and/or Q_(BB).

The adjustments to the power levels and/or time adjustments for the input signals may be referred to as distortion of the digital signals, I_(BB) and/or Q_(BB), which may provide compensation for estimated AM-AM and/or AM-PM distortion of signals in the PA 214. These compensatory adjustments on the digital signals may, therefore, be referred to as a digital predistortion scheme, which may be practiced in various embodiments of the invention. In various embodiments of the invention, the digital predistortion scheme may enable a method and system for compensating for estimated distortion from a PA 214 resulting from limitations imposed by various semiconductor fabrication technologies, for example 65 nm CMOS. Various embodiments of the invention may provide a method and system for compensating for estimated distortion from a PA 214 integrated into an RF transmitter 123 b on a single IC 200.

In various embodiments of the invention, the selected semiconductor fabrication technology, for example 65 nm CMOS, may enable integration of the PA 214 with an RF transmitter 123 b in a single IC 200. In turn, the integration of the PA 214 within an RF transmitter 123 b, which is integrated in the same IC 200 with the signal attenuation block 218, feedback mixer 220, and RF receiver 123 a, may enable a means by which the signal attenuation block 218 may receive differential input signals from the PA 214, and adjust the level of attenuation of the input signal at the signal attenuation block 218 under control of the baseband processor 240.

In various embodiments of the invention, the feedback signal from the PA 214 utilizes at least a portion of the circuitry in the RF receiver 123 a to send the feedback signals I_(FB) and/or Q_(FB) to the baseband processor 240. The approach differs from an approach in which the feedback path from the PA 214 to the baseband processor 240 utilizes dedicated circuitry. By reusing circuitry in the RF receiver path 123 a, the amount of circuitry required to implement the feedback loop may be reduced, which may consequently reduce IC manufacturing cost, and operating temperature, and/or improve IC reliability and/or performance.

By utilizing a separate feedback mixer 220 in the feedback path, and thereby bypassing the receiver I mixer 226 a and the receiver Q mixer 226 b, the design of receiver I mixer 226 a and the receiver Q mixer 226 b to be optimized for receipt of RF signals that are received via the antenna 121 and amplified by the RFLNA 224. Furthermore, the range of attenuation levels applied at the signal attenuation block 218 to input signals from the PA 214 may be selected to provide signal levels suitable for the feedback mixer 220, for example to enable linear performance in the feedback mixer 220. The feedback mixer 220 may then be optimized for receipt of input signals that comprise the range of signal power levels that may be output from the signal attenuation block 218. In various embodiments of the invention, a single feedback mixer 220 may be utilized to mix down the attenuated signal from the PA 214, which may then be inserted as a feedback signal in the RF receiver path 123 a. In an exemplary embodiment of the invention, the insertion point in the RF receiver path 123 a may be inputs to the I HPVGA 228 a and/or Q HPVGA 228 b.

In various embodiments of the invention, the feedback signal sent from the PA 214 to the feedback mixer 220 may be based on a signal comprising data transmitted from the RF transmitter 123 b, for example OFDM symbols generated by the baseband processor 240 and transmitted in a WLAN network. In this case, calibration may be performed concurrently while the RF transmitter 123 b is transmitting data. In other embodiments of the invention, the feedback signal may be based on a continuous wave signal, for example a sine wave signal generated by the baseband processor 240.

FIG. 3A is a graph illustrating an exemplary AM-AM distortion response in a transmitter power amplifier circuit, in accordance with an embodiment of the invention. Referring to FIG. 3A, there is shown an AM-AM distortion response curve 302, an ideal PA response curve 304, and an asymptotic output signal power level curve 306. In the exemplary graph shown in FIG. 3A, the horizontal axis represents input power levels, p_(in), as measured in dBm. The input power level, p_(in), may be measured at the outputs from the baseband processor 240 that are input to the I DAC 202 a and/or Q DAC 202 b. The vertical axis represents output power levels, p_(out), as measured in dBm. The output power level, p_(out), may be measured from the output from the PA 214.

In various embodiments of the invention, the AM-AM distortion response curve 302 may be derived by configuring the RF receiver 123 a in the calibration mode and generating input signals from the baseband processor 240 that span a range of input power levels, while measuring the corresponding power levels in the feedback signal received at the baseband processor 240. The AM-AM distortion response curve 302 may comprise a characterization of the AM-AM distortion performance of the PA 214. In the exemplary graph shown in FIG. 3A, the input power level may range from −8 dBm, to 8 dBm, while the output power level may range from about 15.5 dBm to about 26.5 dBm.

For values of output power level in the range from about 15.5 dBm to about 16.5 dBm, the AM-AM distortion response curve 302 may be substantially linear, and the calibration measurements of the PA 214 output performance are approximately equal to the ideal PA response curve 304. Thus, AM-AM distortion may be low for this first range of output power levels.

For values of output power level in the range from about 16.5 dBm to about 21 dBm, the AM-AM distortion response curve 302 begins to diverge from the ideal PA response curve 304. Thus, AM-AM distortion in the PA 214 may increase for this second range of output power levels.

For values of output power level in the range from about 21 dBm to about 26.5 dBm, the AM-AM distortion response curve 302 begins to diverge from the ideal PA response curve 304 by an even greater amount. Within this output power level range, the AM-AM distortion response curve 302 begins to level off at a peak output power level, corresponding to the asymptotic output signal power curve 306. Thus, AM-AM distortion in the PA 214 may increase by an even greater amount for this third range of output power levels.

The baseband processor 240 may utilize the AM-AM distortion response curve 302 to digitally predistort power levels for input signals to compensate for the estimated AM-AM distortion in the PA 214 based on the AM-AM distortion response curve 302. For example, for an input power level of 0 dBm, the intended output power level may be about 24.5 dBm as shown in the ideal PA response curve 304. However, due to AM-AM distortion in the PA 214, the estimated output power level may be about 23.5 dBm as shown in the AM-AM distortion response curve 302.

In various embodiments of the invention, the baseband processor 240 may enable compensation for the estimated AM-AM distortion performance in the PA 214 by adjusting the input power level from 0 dBm to about 1 dBm. Based on the AM-AM distortion response curve 302, the output power level is about 24.5 dBm in response to an input power level of about 1 dBm. Thus, about 1 dBm of digital distortion may be applied to the input signals I_(BB) and/or Q_(BB) from the baseband processor 240 to compensate for the estimated AM-AM distortion performance of the PA 214. The maximum output power level from the PA 214 may be determined by the asymptotic output signal power level curve 306. In the ideal PA response curve 304, the maximum output power level may be generated when the input power level is about 2 dBm. Based on the AM-AM distortion response curve 302, an output power level of about 26.5 dBm may be generated in response to an input power level of about 8 dBm. Thus, about 6 dB of digital distortion may be applied to the input signals I_(BB) and/or Q_(BB) from the baseband processor 240.

FIG. 3B is a graph illustrating an exemplary AM-PM distortion response in a transmitter power amplifier circuit, in accordance with an embodiment of the invention. Referring to FIG. 3B, there is shown an AM-PM distortion response curve 312, a minimum output phase curve 314, and a maximum output phase curve 316. In the exemplary graph shown in FIG. 3B, the horizontal axis represents input power levels, p_(in), as described in FIG. 3A. The vertical axis represents output phase, φ_(out), as measured in degrees. The output phase may be derived based on a time delay between a time instant corresponding to generation of an input signal from the baseband processor 240, and a time instant corresponding to generation of a corresponding output signal from the PA 214.

In various embodiments of the invention, the AM-PM distortion response curve 312 may be derived by configuring the RF receiver 123 a in calibration mode and generating input signals from the baseband processor 240 that span a range of input power levels. For each input signal generated at a specified input power level, an input time instant may be determined, and a corresponding time instant determined based on the time instant at which the corresponding feedback signal may be received at the baseband processor 240. The AM-PM distortion response curve 312 may comprise a characterization of the AM-PM distortion performance of the PA 214.

In the exemplary graph shown in FIG. 3B, the input power level may range from −8 dBm to 8 dBm, while the output phase may range from a minimum phase value of about 28° to a maximum phase value of about 38°. The minimum phase value may be represented by the minimum output phase curve 314, while the maximum phase value may be represented by the maximum output phase curve 316. The AM-PM distortion may be observed in the graph 312 when the output phase level changes in response to a change in the input power level.

In various embodiments of the invention, the baseband processor 240 may utilize the AM-PM distortion curve 312 to digitally predistort input signals generated by the baseband processor 240 by adjusting the time instant at which the signals are generated, in relation to a scheduled time instant, such that the output phase φ_(out) is approximately constant for a range of input power levels. The constant output phase level may be referred to as a target output phase level.

In an exemplary embodiment of the invention, the baseband processor 240 may utilize the minimum phase curve 314 to determine that the target output phase level is to be about 28°. For an input power level of 0 dBm, the target output phase level may be 28°, however, due to the AM-PM distortion in the PA 214, the estimated output phase may be about 36° as shown in the AM-PM distortion response curve 312.

The baseband processor 240 may utilize the minimum phase curve 314 to enable compensation for the estimated AM-PM distortion performance in the PA 214 by adjusting the time instant at which the input signal is generated by generating the input signal at time instant, which is earlier in time than the scheduled time instant t₀. The corresponding time offset may be referred to as Δt_(−0dBm), wherein the adjusted time instant, t_(adj), may be represented as in the following equation: t _(adj) =t ₀ −Δt _(−0dBm)  [1] where the value Δt_(−0dBm) may correspond to approximately 8° of AM-PM distortion in the PA 214.

In another exemplary embodiment of the invention, the baseband processor 240 may utilize the maximum phase curve 316 to determine that the target output phase level is to be about 38°. For an input power level of 0 dBm, the target output phase level may be 38°.

The baseband processor 240 may utilize the maximum phase curve 316 to enable compensation for the estimated AM-PM distortion performance in the PA 214 by adjusting the time instant at which the input signal is generated by generating the input signal at time instant, which is later in time than the scheduled time instant t₀. The corresponding time offset may be referred to as Δt_(+0dBm), wherein the adjusted time instant, t_(adj), may be represented as in the following equation: t _(adj) =t ₀ +Δt _(+0dBm)  [2] where the value Δt_(−0dBm) may correspond to approximately 2° of AM-PM distortion in the PA 214. Comparable time adjustments may be made for input signals generated for other input power levels based on the AM-PM distortion response curve 312, and a given target output phase level.

Various embodiments of the invention may be utilized to determine the target output phase level, which may not be restricted to a maximum and/or minimum value in the AM-PM distortion response curve 312.

The AM-AM distortion and/or the AM-PM distortion comprise transmitter impairments that may result in signal transmission errors that may result in unintentional and/or undesirable modifications in the magnitude and/or phase of transmitted signals. When transmitting quadrature RF signals, the AM-AM distortion and/or the AM-PM distortion may cause unintentional and/or undesirable modifications in the magnitude and/or phase of the I components and/or Q components in the transmitted signals.

The transmission of erroneous signals from an RF transmitter 123 b may result in erroneous detection of data contained within the received signals at an RF receiver 123 a. The result may be reduced communications quality as measured, for example, by packet error rate (PER), and/or bit error rate (BER).

Communications standards may specify a limit for EVM in a transmitted signal. For example, various standards for WLAN communications may specify that EVM_(dB) for a transmitted signal may be no greater than −25 dB. Thus, some conventional RF transmitters may be required to limit the peak power level for signals generated by the PA 214 to ensure that the transmitted signals comply with EVM specifications. For example, with reference to FIG. 3A, an EVM specification may limit a conventional RF transmitter to a peak power level of about 22 dBm based on the difference in the output power level in graph 302 and graph 304 at an input power level of about −2 dBm. One potential limitation imposed by the reduced output power level is the reduced operating range in wireless communications. In this regard, the EVM specification may reduce the allowable distance between a transmitting antenna and a receiving antenna for which signals may be transmitted from an RF transmitter 123 b and received by an RF receiver 123 a, in relation to the operating range that would be theoretically possible if the RF transmitter 123 b were able to transmit signals at the maximum, or saturation, output power level that could be generated by the PA 214.

In various embodiments of the invention, however, digital predistortion may be utilized to enable compensation of transmitter impairments in the PA 214 such that the PA 214 may be able to transmit signals at higher average output power levels while still complying with relevant EVM specifications, for example. In an exemplary case described above, digital predistortion may be utilized to enable an RF transmitter 123 b to transmit signals at the saturation output power level by applying about 6 dB of digital predistortion to an input signal, for which the input power level may be about 2 dBm, to compensate for estimated AM-AM distortion in the PA 214.

FIG. 4 is a flow chart illustrating an exemplary calibration method for estimating distortion in a transmitter, in accordance with an embodiment of the invention. FIG. 4 refers to a calibration method, which may be utilized to generate an AM-AM distortion response curve 302, and/or AM-PM distortion response curve 312. Referring to FIG. 4, in step 402, the baseband processor 240 may configure the I path selector switch 234 a, and/or Q path selector switch 234 b, to send a feedback signal to the baseband processor 240, which may be based on a PA 214 output signal that was generated in response to an input signal from the baseband processor 240. The feedback signal may be inserted in the RF receiver path 123 a at an input to the I HPVGA 228 a and/or Q HPVGA 228 b.

In step 404, the baseband processor 240 may select a range of input power level values to be utilized during the calibration procedure. In addition, the baseband processor 240 may configure the signal attenuation block 218 to insert a specified level of signal attenuation in the signal received from the PA 214 before sending the attenuated signal to the feedback mixer 220.

In step 406, the baseband processor 240 may select an input power level from the input power level range specified in step 404. The baseband processor 240 may generate an input signal that may be sent to the I DAC 202 a and/or Q DAC 202 b. The baseband processor may store information related to the input power level the input signals in addition to information related to the time instant at which the input signals were generated. In step 408, the signal attenuation block 218 may attenuate the signal received from the PA 214, utilizing a level of signal attenuation determined in step 404. In step 410, the feedback mixer 220 may mix down the attenuated signal to generate a mixed down output signal.

In step 412, the baseband processor 240 may measure the output power level at the PA 214 based on the received feedback signal. In step 416, the baseband processor 240 may store the input amplitude level, corresponding output amplitude level, and corresponding output phase level. In step 418, the baseband processor 240 may determine if there are additional input power levels to be selected to enable generation of the AM-AM distortion response curve 302 and/or AM-PM distortion response curve 312. If the current input power level is the last input power level in the input power level range selected in step 404, then in step 420 the predistortion function may be calculated by the baseband processor 240. In step 422, the predistortion function may be applied to baseband signals generated by the baseband processor 240. In step 424, an RF signal, generated in response to the predistorted baseband signal, may be transmitted by the RF transmitter 123 b. If there are remaining input power levels in the input power level range at step 418, then a subsequent input power level may be selected in step 406.

FIG. 5 is a flow chart illustrating an exemplary calibration method for estimating distortion in a transmitter for modulated data, in accordance with an embodiment of the invention. FIG. 5 refers to a calibration method, which may be utilized to generate an AM-AM distortion response curve 302, and/or AM-PM distortion response curve 312 when utilizing modulated signals. Referring to FIG. 5, in step 502, the baseband processor 240 may configure the I path selector switch 234 a, and/or Q path selector switch 234 b, to send a feedback signal to the baseband processor 240, which may be based on a PA 214 output signal that was generated in response to an input signal from the baseband processor 240. The feedback signal may be inserted in the RF receiver path 123 a at an input to the I HPVGA 228 a and/or Q HPVGA 228 b.

In step 504, the baseband processor 240 may select a modulated signal power level range to be utilized during the calibration procedure. An exemplary modulated signal is an OFDM signal. In addition, the baseband processor 240 may configure the signal attenuation block 218 to insert a specified level of signal attenuation in the signal received from the PA 214 before sending the attenuated signal to the feedback mixer 220.

In step 506, the signal attenuation block 218 may attenuate the signal received from the PA 214, utilizing a level of signal attenuation determined in step 504. In step 508, the baseband processor 240 may measure the output phase and amplitude distortions in received feedback signals. In step 510, a predistortion function may be calculated by the baseband processor 240. In step 512, the predistortion function may be applied to baseband signals generated by the baseband processor 240. In step 514, an RF signal, generated in response to the predistorted baseband signal, may be transmitted by the RF transmitter 123 b. Steps 508-514 may be periodically repeated to recalibrate the RF transmitter 123 b. The recalibration may be performed while transmitting modulated signals.

Aspects of a system for compensating for estimated distortion in a transmitter by utilizing a digital predistortion scheme with a single feedback mixer may comprise an RF transmitter 123 b that enables generation of an output signal in response to one or more generated input signals. A feedback signal may be generated within a single feedback mixer circuit 220 that may perform a frequency mix-down operation on the generated output signal. The generated feedback signal may be inserted at one or more insertion points in an RF receiver 123 a. Each of the insertion points may be located between a mixer stage of the RF receiver 123 a, and one or more circuits that generate baseband signals I_(FB) and/or Q_(FB) based on the generated feedback signal.

The signal attenuation block 218 may enable performance of the frequency mix-down operation on an attenuated version of the generated output signal. The signal attenuation block 218 may enable selection of an attenuation level for generating the attenuated version of the generated output signal. The I path selector switch 234 a and/or Q path selector switch 234 b may enable configuration of the RF receiver 123 a for insertion of the generated feedback signal.

The feedback mixer circuit 220 may enable selection of a frequency for the frequency mix-down operation. The selected frequency may be a local oscillator frequency utilized by the single feedback mixer circuit 220.

The baseband processor 240 may enable generation of a plurality of I_(BB) and Q_(BB) input signals and reception of a corresponding plurality of generated baseband signals I_(FB) and Q_(FB). Each of the generated I_(BB) and Q_(BB) input signals may comprise a distinct input power level.

The baseband processor 240 may enable estimation of an output power level for an output signal generated by the PA circuit 214 based on the generated feedback signal from the feedback mixer circuit 220 for each of the corresponding distinct input power levels of the generated I_(BB) and Q_(BB) input signals. The baseband processor 240 may enable estimation of amplitude distortion in the generated output signal generated by the PA circuit 214 based on the estimated output power level and a corresponding distinct input power level for the generated I_(BB) and/or Q_(BB) input signals.

The baseband processor 240 may enable estimation of an output time instant for the generated output signal from the PA circuit 214 in relation to an input time instant for the generated I_(BB) and/or Q_(BB) input signals based on the feedback signal generated by the feedback mixer circuit 220 for each corresponding one or more distinct input power level. The baseband processor 240 may enable estimation of phase distortion in the generated output signal based on the estimated output time instant, the input time instant and the corresponding distinct input signal level for the I_(BB) and/or Q_(BB) input signals.

Accordingly, the present invention may be realized in hardware, software, or a combination of hardware and software. The present invention may be realized in a centralized fashion in at least one computer system, or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware and software may be a general-purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein.

The present invention may also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which when loaded in a computer system is able to carry out these methods. Computer program in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to another language, code or notation; b) reproduction in a different material form.

While the present invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims. 

What is claimed is:
 1. A system implemented in a single chip, comprising: a feedback mixer circuit configured to perform a frequency mix-down operation on an output signal of a radio frequency (RF) transmitter to generate a feedback signal; and a plurality of selector switches configured by a processor to insert, during a calibration mode, the generated feedback signal at insertion points in an RF receiver corresponding to in-phase (I) and quadrature-phase (Q) components of the output signal by configuring a closed feedback loop comprising the RF transmitter and a portion of the RF receiver defined by the insertion points.
 2. The system of claim 1, wherein the processor is configured to compensate for at least one of amplitude modulation to amplitude modulation (AM-AM) distortion or amplitude modulation to phase modulation (AM-PM) distortion of the power amplifier utilizing the plurality of selector switches.
 3. The system of claim 1, further comprising a signal attenuator configured to attenuate the output signal and transmit the attenuated output signal to the feedback mixer circuit.
 4. The system of claim 3, wherein the signal attenuator is configured to attenuate the output signal based on a linear operating range of the feedback mixer circuit.
 5. The system of claim 3, wherein the signal attenuator is configured to attenuate the output signal at a level specified by the processor.
 6. The system of claim 1, wherein the plurality of selector switches is configured by the processor to disable the closed feedback loop configuration during a normal operating mode.
 7. The system of claim 1, wherein the closed feedback loop includes a power amplifier of the RF transmitter.
 8. A method, comprising: generating an output signal of a radio frequency (RF) transmitter in a chip, in response to an input signal; performing a frequency mix-down operation on the output signal to generate a feedback signal; and selectively inserting, during a calibration mode, the generated feedback signal at insertion points in an RF receiver in the chip, the insertion points corresponding to in-phase (I) and quadrature-phase (Q) components of the output signal by configuring a closed feedback loop comprising the RF transmitter and a portion of the RF receiver defined by the insertion points.
 9. The method of claim 8, wherein generating the feedback signal is performed across distinct power levels of the input signal.
 10. The method of claim 9, further comprising estimating an output power level for each generated output signal based on the corresponding feedback signal for each distinct input power level.
 11. The method of claim 10, further comprising estimating amplitude distortion in each generated output signal based on: the estimated output power level and corresponding input power level.
 12. The method of claim 8, comprising performing the frequency mix-down operation on an attenuated version of the generated output signal.
 13. The method of claim 12, comprising selecting an attenuation level for generating the attenuated version of the generated output signal.
 14. The method of claim 8, comprising selecting a frequency for the frequency mix-down operation.
 15. The method of claim 8, wherein the closed feedback loop includes a power amplifier of the RF transmitter.
 16. A radio frequency (RF) transceiver in a single chip, comprising: a feedback mixer circuit configured perform a frequency mix-down operation on an output signal of a RF transmitter to generate a feedback signal; and a selection circuit in an RF receiver configured to insert the generated feedback signal at a first insertion point and a second insertion point in the RF receiver by configuring a closed feedback loop comprising the RF transmitter and a portion of the RF receiver defined by the insertion points, wherein the first insertion point corresponds to an output of a first amplifier of the RF receiver and the second insertion point corresponds to an output of a second amplifier of the RF receiver.
 17. The RF transceiver of claim 16, wherein a signal attenuator is configured to attenuate the output signal based upon a specified attenuation level.
 18. The RF transceiver of claim 16, comprising a processor that configures the selection circuit to insert, during a calibration mode, the generated feedback signal at the first and second insertion points.
 19. The RF transceiver of claim 18, wherein the processor is further configured to estimate amplitude distortion in the generated output signal based upon an estimated output power level and a corresponding input power level.
 20. The RF transceiver of claim 18, wherein the processor is further configured to estimate phase distortion in the generated output signal based upon an estimated output time instant, an input time instant, and a corresponding distinct input signal level. 